UMX FLIP Installation Guide download pdf (Page 29)

Chapter 3.

Sora Fundamentals

3.1 Architecture

The overall system architecture of Sora is illustrated in Figure 7. The RCB interconnects RF front-

ends to the PC. The RCB talks to the PC using the PCI-E interface, and with read/write digital

signal samples from/to PC memory using direct memory access (DMA). It connects to the RF

front-end boards with the Sora Fast Radio Link (SoraFRL). SoraFRL defines the necessary

protocol for the RCB to control the RF boards. Any Sora compatible RF boards should implement

SoraFRL. For more information on SoraFRL, please refer to the “Sora Fast Radio Link

Specification”.

Figure 7. Sora System Architecture.

Figure 8 shows the Sora software architecture. The RCB driver manages the RCB and RF front-

end hardware resources and provides APIs to the SDR miniport driver to send/receive digital

waveform samples. The SDR miniport driver usually exposes an Ethernet interface to the

operating system, so that all network applications can seamlessly use it for communication. In

Sora SDK, a sample SDR miniport driver, named SoftWiFi, is provided, which implements the

Mem

Sora

APP

Multi-core CPU

Software Radio Stack

High throughput

low latency PCIe bus

Digital Samples

@Multiple Gbps

RCB

A/D

D/A

Sora

APP

Commodity PC

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UMX FLIP Installation Guide Page 29